About the Role
We are looking for talented and driven CPU Subsystem (CPUSS) Design Verification Engineers and Leads to join a world-class semiconductor engineering team across Bangalore and Hyderabad. This is a Work From Office (WFO) role offering an outstanding opportunity to work on next-generation RISC-V based CPU architectures, covering everything from pipeline unit verification to complex cache coherency validation. Whether you are an individual contributor or a seasoned lead, this role promises deep technical challenge and high visibility across the chip design lifecycle.
Key Responsibilities
- Design, develop, and maintain SystemVerilog/UVM-based testbench environments for CPU and cache subsystems
- Develop and debug assembly-level tests targeting CPU pipeline and subsystem functionality
- Perform comprehensive cache verification including memory consistency, CHI protocol, coherence manager, and shared L1/L2/L3 cache hierarchies
- Verify CPU pipeline units — Fetch, Decode, Schedule, Execute — and Load/Store unit functionality
- Validate vector datapath operations for both functional correctness and performance
- Drive verification coverage aligned with RISC-V (RVA23) architecture standards
- Collaborate cross-functionally with RTL design, architecture, and simulation teams to debug failures across testbenches and simulations
Requirements
- 5–20 years of experience in Design Verification, with a focus on CPU and/or cache subsystems
- Strong hands-on expertise in SystemVerilog and UVM testbench development
- Proven experience debugging and writing assembly tests for CPU verification
- Deep understanding of cache coherency protocols (CHI, MESI, or equivalent) and shared cache architectures
- Solid verification experience with RISC-V architecture, preferably RVA23 standards
- Familiarity with vector datapath verification for correctness and performance validation
- Strong debugging, analytical, and cross-functional collaboration skills
- Prior Lead experience preferred for senior applicants — ability to drive verification planning and team execution