About the Role
We are seeking experienced Design for Test (DFT) Engineers to join a cutting-edge semiconductor team in Bangalore. This role offers deep engagement across the full DFT lifecycle — from RTL insertion and scan stitching through ATPG pattern generation and post-silicon validation. If you are a detail-oriented engineer with a passion for testability architecture and silicon quality, this is an exceptional opportunity to work on complex SoC designs with industry-leading methodologies.
Key Responsibilities
- Perform RTL DFT insertions and verification across block and SoC levels
- Implement and validate SSN (Scan Segment Network) architectures
- Execute IJTAG (IEEE 1687) insertion and verification at both block and SoC levels
- Drive MBIST insertion, memory repair configuration, and verification across block and SoC
- Implement and validate EDT-based scan compression flows
- Perform netlist insertions and pattern verification
- Execute gate-level scan stitching and Design Rule Check (DRC) validations
- Implement and validate LBIST architectures
- Generate ATPG patterns (stuck-at and transition) and run Gate-Level Simulations (GLS)
- Perform coverage analysis, debug, and pattern optimization
- Support post-silicon bring-up, ATE integration, and silicon debug activities
Requirements
- 8–15 years of hands-on DFT engineering experience in semiconductor/SoC environments
- Strong proficiency in RTL and netlist-level DFT insertion flows
- Solid experience with IJTAG (IEEE 1687), MBIST, SSN, and EDT scan compression
- Hands-on expertise in ATPG pattern generation (stuck-at/transition) and GLS simulations
- Experience with LBIST architecture design and validation
- Strong understanding of gate-level scan stitching and DRC checks
- Proven ability to support ATE environments and post-silicon debug
- Excellent analytical, debugging, and cross-functional collaboration skills